1. Technical Field
The invention relates to the transfer of information in an electronic network between system elements having different data transfer rates. More particularly, the invention relates to a three port FIFO data buffer having multi-level caching.
2. Description of the Prior Art
Various data transfer techniques have evolved as the need to move information, in terms of both speed and quantity, has increased. One promising technique is provided by the Firewire (IEEE 1394) specification. Proposed actual data rates (i.e. independent of any encoding scheme) for Firewire are in multiples of .about.100 Mbit/s.
While Firewire provides a synchronous serial bus having a data transfer rate of .about.43 Mbit/s, other protocols that may be provided in a common system with Firewire have different data transfer characteristics. For example, VME/VXI provides an asynchronous parallel bus having a data transfer rate of 0-80 Mbit/s.
It is not possible, in general, to transfer data directly from a device on a first of the foregoing buses, over the first bus itself, through a direct interface and over a second bus, to a target device on the second bus. In addition, the packet oriented protocol of Firewire (IEEE 1394) includes CRC verification for each packet which may be inconsistent with other protocols.
To accommodate such data transfer, the interface device must incorporate at least some buffering capability.
It would be advantageous to provide a data buffer that is flexible enough to handle high speed data transfers between the buses, configuration messages between a Firewire controller device and the interface device control processor, character string translations from Firewire packets to VXI bus message based protocol transfers, and asynchronous interrupts from VME/VXI devices to a Firewire controller.